Industry Leaders Drive Phased Implementation and Interoperability Testing of SystemVerilog Design and Assertion Constructs
SAN JOSE, Calif.—(BUSINESS WIRE)—May 14, 2004—
Leading EDA companies and experts announce the formation
of a SystemVerilog Implementation Working Group to drive the phased
implementation and multi-vendor interoperability of the design and
assertion constructs of SystemVerilog. EDA vendors include Cadence
Design Systems, Inc. (NYSE:CDN); Magma Design Automation Inc.
(Nasdaq:LAVA); Novas Software; 0-In Design Automation, Verisity Ltd
(Nasdaq:VRST), and industry experts and consultants Stuart Sutherland
and Simon Davidmann. User companies participating in the group include
ARC International, Conexant Systems, Inc., Icera Semiconductor and
Micronas GmbH. For more information, and to register for a
SystemVerilog Interoperability Forum at the 41st Design Automation
Conference (DAC) in San Diego, CA, please visit
www.sutherland-hdl.com/sv_interop.
Contact:
The Hoffman Agency (Public Relations for Cadence)
Kristin Hehir, 408-975-3098
khehir@hoffman.com
or
Skye Marketing Communications
(Public Relations for Simon Davidmann)
Leslie Cumming, 650-594-4307
leslie@skyecommunications.com
or
Magma Design Automation Inc.
Monica Marmie, 408-565-7689
monical@magma-da.com
or
Wired Island, Ltd. (Public Relations for Novas)
Laurie Stanley, 510-656-0999
laurie@wiredislandpr.com
or
0-In Design Automation
Richard Ho, 408-487-3647
richard@0-in.com
or
Sutherland HDL
Stuart Sutherland, 503-692-0898
stuart@sutherland-hdl.com
or
Verisity Design, Inc.
Jennifer Bilsey, 650-934-6823
jen@verisity.com
